Virtex-4
Xilinx Details Its Next Generation

In the 90s, it was obvious that within the decade, exploding gate counts would outstrip our ability to design. The popular debate topic at that time was how the “white space” would be used. “White space” represented the difference between the number of available gates on a semiconductor device, and the number of gates we could successfully design correctly using current methodologies. Speculation ran rampant that large amounts of RAM, immense IP blocks, and system-on-chip integration would help us fill some of the space, but the overall question remained.

When FPGAs burst onto the scene, few noticed that they were quietly answering the "white space" question. By introducing a 5-10X area penalty for the privilege of programmability, FPGAs brought the whole problem down to earth again by providing us with a much safer, more practical, and more versatile implementation fabric that was unfortunately also about a decade back on the Moore’s Law trail. Suddenly, with programmable logic design, our old friends power, performance, and price were problems again and we no longer had to worry about “white space.” Instead, we had a new problem: “the gap.”

“The gap” is the area in-between FPGA and ASIC. On the FPGA side of “the gap” we have time-to-market, zero NRE cost, flexibility, upgradeability, low risk, cheap design tools, and a host of other benefits. On the ASIC side we have power, performance, unit price and functionality that cannot yet be duplicated on FPGA. In between, where the sweet spot probably lies for many, many applications, is “the gap”.

Today, on each side of “the gap” there is a race toward center. Semiconductor vendors on both sides are pushing toward that sweet spot, trying to win over the lucrative middle-ground market. With high-end cell-based ASIC only being for the strong of heart and pocketbook, and FPGAs only for those with low production volumes and high power budgets, an alternative is needed that offers less risk, faster time-to-market and lower development cost than ASIC; with more performance, lower unit cost, and higher density than FPGAs. [more]

Racing for the Gap
Altera and Synopsys go Structured

As suppliers jockey for position in offering products that hit the gap between the flexibility and risk-free design offered by FPGA and the performance and unit-cost advantages of cell-based ASIC, unlikely alliances are inevitable. In this case, ASIC design tool leader Synopsys is teaming with leading FPGA vendor Altera to jointly develop solutions for the design and production of Structured ASICs.

Altera has long touted their HardCopy structured ASIC as a clean cost-reduction path from an FPGA-based development, prototype, and early production platform to a cost-reduced, performance-optimized mask-programmed equivalent. Altera is betting that the advantages of programmable logic for early development will compel design teams to consider their structured ASIC offering.

The announcement this week says that Synopsys’s Galaxy design platform can now target Altera FPGA devices and their HardCopy structured ASIC counterparts, and that Synopsys Professional Services will support Altera’s HardCopy design centers. The partnership with Synopsys means that design teams already using Synopsys tools for ASIC design will have one less barrier to adopting an FPGA design methodology for future projects.

As Altera and other FPGA vendors diversify beyond their traditional applications and customer base, they are seeking ways to reduce unit cost, increase performance, and cut power consumption taking them closer to the capabilities of high-end ASIC while maintaining their substantial advantages in risk, schedule, flexibility, and design-cost. Altera’s strategy is somewhat unique among FPGA vendors as they are taking a mask-programmed approach similar to the ASIC suppliers rather than focusing on reducing the cost of a programmable logic fabric like rival Xilinx has with their Virtex-4 platform announced this week. [more]